Netlist

PACKAGES

1206 ! 1206 ! '.1' ; C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 C18 , C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 , C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 , C53 C54 C55 C56 C57 C58 C60 C61 C62 C63 C64 C65 C66 C67 C68

1206 ! 1206 ! 1K ; R9 R21 R30 R31 R32 R34 R35 R36 R37 R38 R39 R51 R61 R62

1206 ! 1206 ! 22 ; R25 R26 R27 R40

1206 ! 1206 ! 33 ; R20 R29 R44 R53

1206 ! 1206 ! '4.7K' ; R11 R22 R28 R33 R43 R45 R50 R52 R54 R55 R56 R57 R58 , R59 R60 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79

6032 ! 6032 ! '4.7' ; C59

7343 ! 7343 ! 22UF ; C2 C15

CON20 ! CON20 ; P3

CON50 ! CON50 ; P6

CON60 ! 'IDC-60F' ; P1

DB9 ! DB9 ; P2

'HALF-OSC' ! 25MHZ ; U3

HDR2X5 ! HDR2X5 ; P5

JMP3 ! JMP3 ! 'HEADER 3' ; JP22

LL34 ! 1N4148 ; D19

PLCC20 ! 75ALS053 ; U26 U27

PLCC32S ! AM29F040 ; U7 U16 U21

PQFP100 ! XC5204 ; U17

PQFP160 ! POWERPC403GA ; U15

PQFP208 ! XC4013 ; U9 U23

PWRCON ! PWRCON ; J1

SIMM72 ! HB56D236B ; U2

SO16 ! MAX232A ; U25

SO20 ! 74ACT240 ; U30

SO20 ! 74ACT244 ; U8

SO24 ! 74BCT8245 ; U13 U19

SO24 ! 74BCT8374A ; U5

SO28W ! IDT7201LA35SO ; U22

SO8 ! 75462 ; U28

SO8 ! TL7705ACD ; U32

SOJ28 ! IDT71256SA ; U6 U11 U14 U20

'SWDIP-8' ! 'SWDIP-8' ; S21

SWITCH ! SWSPST ; S23

TQFP100 ! EP7128 ; U12

TQFP44 ! MACH111SP ; U4

TQFP44 ! XC9536 ; U18

$NETS

A5 ; RN2.16 U4.2 U11.27 U23.122

A6 ; RN2.15 U4.1 U23.123

A7 ; RN2.14 U4.44 U23.124

A8 ; RN2.13 U4.43 U23.125

A9 ; RN2.12 U4.42 U23.126

A10 ; RN2.11 U4.41 U23.127

A11 ; RN2.10 S4.2 U4.40 U23.128

A12 ; RN2.9 U4.37 U23.129

A13 ; P6.16 U6.1 U7.1 U11.1 U14.1 U15.99 U20.1 U23.132

A22_A ; R78.2 S12.3 U11.5

AMUXCAS ; U15.139 U23.75

BA24 ; U10.2 U12.76 U18.30

BA25 ; U10.3 U12.75 U18.29

BA26 ; U10.4 U12.72 U18.28

BA27 ; U10.5 U12.71 U18.27

BA28 ; U10.7 U12.70 U18.23

BA29 ; U10.8 U12.69 U18.22

BA30 ; U10.9 U12.68 U18.21

BD6 ; S7.2 U12.78 U13.16 U18.32

BD7 ; S7.1 U12.77 U13.15 U18.31

'BUSERROR*' ; RN4.12 U15.12 U23.44

'BUSREQ/DMADXFER*' ; U15.135 U23.98

B_TCK ; JP3.1 JP17.2 U4.7 U5.13 U9.9 U10.13 U12.62 U13.13 U15.6 U17.8 , U18.11 U19.13

B_TMS ; JP4.2 JP5.1 JP6.1 JP9.1 R52.1 S1.2 U5.12 U9.17 U12.15 U17.9 U18.10 , U19.12

'C1+' ; C24.1 U25.1

'C1-' ; C24.2 U25.3

'C2+' ; C21.1 U25.4

'C2-' ; C21.2 U25.5

'CAS0*' ; S6.2 U2.42 U15.142 U23.76

'CAS1*' ; S6.1 U2.41 U15.143 U23.80

'CAS2*' ; U2.43 U15.144 U23.81

'CAS3*' ; U2.40 U15.145 U23.82

CCLK ; R29.2 U9.153 U23.153

CE ; P4.1 R22.2 U9.42

CLK ; R29.1 U17.77

CPU_TDO ; JP7.2 JP13.2 U15.8

CPU_TMS ; JP9.2 JP10.2 U15.7

'CS0*' ; P6.7 R61.2 U7.22 U15.155 U23.36

'CS1*' ; U6.20 U11.20 U14.20 U15.154 U20.20 U23.89

'CS2*' ; R53.1 S14.2 U5.1 U23.88

'CS3*' ; R44.1 S16.1 U4.3 U13.24 U22.1 U23.87

'CS4*/RAS3*' ; U15.151 U23.86

'CS5*/RAS2*' ; U15.148 U23.85

'CS6*/RAS1*' ; U15.147 U23.84

'CS7*/RAS0*' ; U2.33 U2.34 U2.44 U2.45 U15.146 U23.83

CT ; C59.1 U32.3 CTS ; P2.6 U25.8

'CTS*' ; U15.28 U25.9

D0 ; P6.6 S3.1 U2.64 U5.15 U7.21 U13.2 U15.42 U20.19 U22.24 U23.72

D1 ; P6.5 S3.2 S4.1 U2.62 U5.16 U7.20 U13.3 U15.43 U20.18 U22.25 U23.71

D2 ; P6.4 S13.2 U2.60 U5.17 U7.19 U13.4 U20.17 U22.26 U23.70

D3 ; P6.3 U2.58 U5.19 U7.18 U13.5 U15.45 U20.16 U22.27 U23.69

D4 ; P6.2 S11.3 U2.56 U5.20 U7.17 U13.7 U15.46 U20.15 U23.68

D5 ; P6.41 S9.2 U5.21 U7.15 U13.8 U15.47 U20.13 U22.4 U23.35

D6 ; P6.40 U2.52 U5.22 U7.14 U13.9 U15.48 U20.12 U22.5 U23.33

D7 ; P6.39 U2.50 U5.23 U7.13 U13.10 U15.51 U20.11 U22.6 U23.64

D5_A ; R73.2 S9.3 U2.54

DELAY1 ; U8.4 U8.18

DELAY_OUT ; S20.1 U8.12

DLY_NET ; S20.3 U8.2 U23.114

DMAR0 ; RN4.1 U15.2

DONE ; R38.2 U8.11 U9.103 U16.22 U16.24 U17.53 U23.103

DOUT1 ; U17.76 U23.151

DOUT2 ; U9.151 U23.152 EA17 ; U16.30 U17.6

'EF*' ; U17.10 U22.21

EOT0 ; RN4.5 U15.128

EOT1 ; RN4.6 U15.131

EOT2 ; RN4.7 U15.132

EOT3 ; RN4.8 U15.133

ERROR ; U15.136 U23.120

FA0 ; U21.12 U23.184

FA1 ; U21.11 U23.185

FA2 ; U21.10 U23.186

FA3 ; U21.9 U23.187

FD6 ; U21.20 U23.28

FD7 ; U21.21 U23.27

'FF*' ; U17.12 U22.8

FIFOD0 ; U17.13 U22.19

FIFOD1 ; U17.16 U22.18

FIFOD7 ; U17.22 U22.9

'FIFORD*' ; U16.20 U17.58

'FIFORST*' ; U16.21 U17.56

GND ; C1.2 C2.2 C3.2 C4.2 C5.2 C6.2 C7.2 C8.2 C9.2 C10.2 C11.2 C12.2 C13.2 , C14.2 C15.2 C16.2 C18.2 C19.2 C20.2 C23.2 C25.2 C26.2 C27.2 C28.2 , C29.2 C30.2 C31.2 C32.2 C33.2 C34.2 C35.2 C36.2 C37.2 C38.2 C39.2 , C40.2 C41.2 C42.2 C43.2 C44.2 C45.2 C46.2 C47.2 C48.2 C49.2 C50.2 , C51.2 C52.2 C53.2 C54.2 C55.2 C56.2 C57.2 C58.2 C59.2 C60.2 C61.2 , C62.2 C63.2 C64.2 C65.2 C66.2 C67.2 C68.2 D4.1 J1.2 J1.3 JP15.1 , JP22.2 P1.5 P1.10 P1.15 P1.20 P1.25 P1.30 P1.35 P1.40 P1.45 P1.50 , P1.55 P1.60 P2.5 P3.1 P3.3 P3.5 P3.7 P3.9 P3.11 P3.13 P3.15 P3.17 , P3.19 P4.3 P4.5 P4.7 P4.9 P5.4 P5.8 P6.1 P6.22 P6.25 P6.26 P6.27 , P6.42 P6.47 P6.48 P6.50 R8.1 R10.1 R30.2 R31.2 R47.2 R49.2 R54.1 , R56.2 R58.1 R62.2 R64.2 R65.2 R70.1 R72.1 R74.1 R76.1 R80.2 S14.1 , S15.2 S16.2 S17.1 S18.2 S21.9 S21.10 S21.11 S21.12 S21.13 S21.14

GPIO ; JP22.1 JP22.3 R9.2 U28.1 U28.2

'HALT*' ; U15.9 U23.45

'HF*' ; U17.11 U22.20

HOLDACK ; U15.134 U23.97

HOLDREQ ; R62.1 U15.14 U23.46

IN0 ; U9.188 U26.3

IN1 ; U9.189 U26.5

IN2 ; U9.190 U26.8

IN3 ; U9.191 U26.10

IN4 ; U9.18 U27.3

IN5 ; U9.19 U27.5

IN6 ; U9.20 U27.8

IN7 ; U9.21 U27.10

'INIT*' ; JP12.2 R45.2 U9.77 U17.39 U23.77

IO14 ; R30.1 U9.198 U26.11

IO23 ; JP3.2 U23.10

IO24 ; JP5.2 U23.11

IO38 ; R31.1 U9.29 U27.11

LED_ALTERA2 ; D8.1 U30.16

LED_ALTERA ; D7.1 U30.18

LED_DRV_ALT2 ; RN3.14 U12.46 U30.4

LED_DRV_ALT ; RN3.15 U12.45 U30.2

LED_DRV_MACH2 ; RN3.8 U4.15 U30.17

LED_MACH ; D5.1 U30.5

LED_XILINX2 ; D18.1 U30.12

LED_XILINX ; D17.1 U30.14

L_TMS ; R68.1 S1.3 U10.12 U13.12

MACH_TMS ; JP6.2 R11.1 U4.26

MCLK ; P3.18 R67.2 R80.1 U26.2

MCTL ; P3.6 R48.2 R49.1 U26.4

MMD ; P3.2 R46.2 R47.1 U27.2

MPR ; P3.10 R63.2 R64.1 U26.7

MSD ; P3.14 R65.1 R66.2 U26.9

OUT5 ; U9.24 U27.17

OUT6 ; U9.27 U27.15

OUT7 ; U9.28 U27.14

PP0 ; S15.1 U18.40 U19.2

PP1 ; U18.41 U19.3

PP9 ; R43.1 U18.7 U19.24

PU2 ; R77.2 S11.2 U22.3

PU3 ; R59.2 U22.2 U22.23

'R/W*' ; U13.1 U15.127 U23.93

READY ; RN4.11 U15.13 U23.43

RECVD ; U15.27 U25.12

REF ; C67.1 U32.1

'RES*' ; R50.2 S23.2 U32.2

'RESET*' ; R51.2 U9.108 U15.91 U17.55 U23.22 U23.108 U32.5

RTS ; P2.4 U25.7

'RTS*' ; U15.88 U23.95 U25.10

RXD ; P2.2 U25.13

TDO_1 ; U17.7 U23.159

TDO_4 ; U18.9 U19.11

TDO_5 ; U12.4 U18.24

TDO_6 ; JP2.2 U12.73 U13.14

TDO_7 ; S2.2 U13.11

TDO_8 ; JP2.1 U5.14 U10.11

TESTC ; R56.1 U15.37

TESTNET ; S20.2 U17.24

TIMERCLK ; RN4.9 U15.25

TMS ; JP4.1 JP8.1 JP10.1 JP11.1 P4.8 P5.3 R36.2

'TN-1' ; U17.59 U22.15

'TN-2' ; U17.88 U22.22

'TN-3' ; JP21.2 U4.29

TRST ; P4.2 R21.2 U9.68

'TRST*' ; U17.96 U23.42

TXD ; P2.3 U25.14

VCC ; C1.1 C3.1 C4.1 C5.1 C6.1 C7.1 C8.1 C9.1 C10.1 C11.1 C12.1 C13.1 C14.1 , C15.1 C16.1 C18.1 C19.1 C22.1 C23.1 C25.1 C26.1 C27.1 C28.1 C29.1 , C31.1 C32.1 C33.1 C34.1 C35.1 C36.1 C37.1 C43.1 C44.1 C45.1 C46.1 , C47.1 C48.1 C49.1 C53.1 C54.1 C55.1 C56.1 C57.1 C58.1 C60.1 C63.1 , C64.1 C65.1 C66.1 K1.8 P5.6 R1.2 R2.2 R3.1 R4.1 R5.2 R6.2 R7.2

'VCS0*' ; S8.2 U4.9

'VCS1*' ; U4.10 U12.48

VDD ; C2.1 C30.1 C38.1 C39.1 C40.1 C41.1 C42.1 C50.1 C51.1 C52.1 C61.1 , C62.1 C68.1 U1.2 U15.20 U15.21 U15.40 U15.49 U15.61 U15.69 U15.80 , U15.89 U15.100 U15.120 U15.129 U15.140 U15.149 U15.160

'VR_W*' ; U4.8 U12.49 U18.8

'WBE0*' ; P6.49 R32.2 U6.27 U7.31 U15.122 U23.121

XMITD ; U15.87 U23.94 U25.11

$END

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